1. Field of the Invention
The present invention relates to the packaging of semiconductor devices, and, more particularly, to the use of thermocompression bonding in the packaging of microelectromechanical systems (MEMS). Accordingly, the general objects of the invention are to provide novel methods and apparatus of such character.
2. Description of Related Art
In the past 15 years, many types of electromechanical sensors have been manufactured using integrated circuit (IC) fabrication techniques. Although they are generally fabricated on silicon wafers, these “microelectromechanical devices” or “MEMS” are different from most ICs in that they possess moving elements. Although MEMS devices are even more vulnerable to contamination and moisture than most ICs, they cannot be encapsulated in a typical injection-molded plastic package because at least one element of every microelectromechanical device must remain free to move. The packaging of MEMS devices, therefore, presents unique problems.
Several specialized methods, which are directed to different stages of the fabrication process, have been employed for the sealing and packaging of MEMS. One early method directed to the final packaging stage employs a ceramic package with a co-fired lead frame, a cavity to contain a complete MEMS chip and lid to cover the package and cavity. With this chip-scale packaging method, the MEMS chip is placed in the cavity and the lid is soldered in place to create a hermetic seal. One problem with this chip-scale packaging approach is the expense associated with handling the individual components (e.g., the packages, lids, etc.) and assembling them into a single package. An additional problem with this chip-scale packaging approach is that the moving elements in MEMS are extremely fragile and tend to be damaged by any handling, especially near the end of the fabrication process. Therefore, packaging yields are typically low. A further problem with this packaging approach is that the solder seal on the lid tends to outgas when reflowed during the final sealing process. If a vacuum is needed inside the package, a getter must be added, at additional cost. In such cases, packaging costs can constitute 80% of the total device cost. In sum, the use of ceramic packages to seal and package MEMS chips is inordinately expensive due to the need to individually handle components, the need to use getters and the considerable opportunity for damage and contamination of the MEMS devices.
A wafer-scale pre-packaging method of bonding two wafers together has been used to bond a wafer of silicon or glass onto a MEMS wafer. In accordance with this process, a non-conductive glass frit is screen-printed onto the lid wafer, in the shape of rings or gaskets. The wafers are then placed together to form cavities containing MEMS devices and bonded by the application of heat in excess of 400 degrees Celsius. After bonding, the two-wafer stack is diced and the resulting hybrid structures are packaged in the standard manner: by encapsulation in plastic packages such as DIPs, SOICs, etc. While this process has been marginally successful, it suffers from the deficiency that the glass frit cannot be patterned into fine features. Typically, gasket pattern line widths are between 100–200 microns. Given that MEMS are currently made with dimensions or features in the one micron size range, significant real estate must be sacrificed, thereby significantly reducing the number of devices that can be fabricated on a single wafer. Attempts have been made to improve the glass frit patterning resolution, using lithographic methods, but these have not shown success. Further, gasket patterns thinner than 100–200 microns in width do not appear to provide reliable hermetic seals, possibly because of the inherently porous nature of glass frits. Thus, it is currently believed that glass frit techniques simply cannot be applied on a smaller scale where hermetic seals are desired.
Glass frit techniques also require high temperatures of between about 450–600 Celsius for sealing to occur. One drawback of using such a high firing temperatures is that it effectively precludes the incorporation of integrated circuitry on either of the wafers bonded together. These temperatures also preclude the use of most anti-stiction coatings and hydrophobic coatings, which are desirable for improving manufacturing yields and MEMS′ tolerance to moisture and shock. Such high temperatures also damage the MEMS themselves and, particularly, certain structural films deposited at lower temperatures and structures in which the film stress must be carefully controlled.
Another deficiency of glass frit techniques is that the glass frit itself employs organic binders, which outgas into the sealed cavity during firing. Since getters are not available to combat this problem, this fact precludes the use of glass frits for vacuum applications. Still another limitation of the glass frit techniques is that the sealing materials, being non-conductive, cannot be used to establish electrical coupling between the devices disposed on the bonded substrates.
Front-end wafer-scale bonding methods which can be used for sealing MEMS have also been described. These methods include anodic bonding, silicon fusion bonding, and other wafer-bonding methods employing combinations of silicon, silicon dioxide, and silicon nitride. These techniques can provide vacuum and hermetic seals and can do so with improved use of chip real estate. However, these processes have low throughput and require high temperatures for high-quality bonds because their bonding mechanisms involve solid diffusion across the bond interface. These methods also place strict constraints on the materials and processes used to form the wafers to be bonded together. Significantly, these methods are also exceptionally sensitive to the presence of even small particulate contaminants, wafer warpage, scratches, and other imperfections commonly encountered during semiconductor fabrication because such contaminants can cause large defects in the bond and reduce yield substantially. Moreover, normal variations in surface topology due to the presence of circuitry can preclude proper bonding and/or sealing using such methods.
Yet another MEMS packaging technique is known as flip-chip technology. This die-scale technique allows a silicon chip to be used as a lid for a microsensor chip. To seal the silicon and microsensor chips together, a ring of solder is patterned on the lid chip and the solder is fused to the silicon chip by the application of heat. Since the solder is relatively thick and liquefies during bonding, this technique is not as sensitive to topography or local defects as thin-film wafer bonding. However, most solders require flux, to ensure consistent bonding. The use of solder to form a seal is not compatible with present MEMS process technologies because MEMS are easily damaged by residual solder flux left after sealing has occurred. While fluxless soldering processes have been attempted, even this approach does not resolve an inherent real-estate inefficiency problem resulting from the fact that the minimum feature size of this solder-based technology is about 100 microns.
Yet another problem with solder-based flip-chip bonding is that special processing is required; not only for fabrication of the solder structures on the lid chip, but also to coat the appropriate areas of the microsensor chip with a solderable metal. Since some standard metals used by commercial IC foundries cannot be soldered directly, solder-based flip-chip technology is still expensive and of limited utility compared to the present invention. Finally, solder-based flip-chip bonding cannot be reliably performed on a wafer-scale because, for example, the normal curvature of processed wafers can exceed the solder bump height. For all of the reasons above, this chip-scale technique is disproportionately expensive relative to wafer-scale packaging/sealing techniques.
Other work in the art has consistently taught that single substrate (monolithic) designs offer the best possible performance in MEMS sensors. According to these sources, minute sensor structures produce very weak (high impedance) signals and, therefore, performance can be maximized by placing an amplifying circuit next to the sensor on the same substrate. The implicit assumption is that any signal coupled off-chip to a separate amplifying circuit would have to go via a bond pad (roughly 100×100 microns) and a bonded wire. Moreover, within the field of MEMS, there is no known reference to the idea of using small bond pads or bumps to reduce parasitic capacitance or otherwise improve the performance of a two-chip (sensor/IC) system. Possibly, this is because manufacturers have confined themselves to standard packaging techniques, such as wirebonding, flip-chip, etc.
Other sources teach that the use of gold is generally avoided in silicon technology because gold forms deep traps in silicon, destroying transistor action. Gold diffuses readily in silicon. For these reasons, gold is not allowed in wafer fabrication facilities. Use of gold in semiconductor packaging is possible, since this occurs after fabrication. MEMS, however, would require additional process steps in a cleanroom following gold deposition. Therefore, many manufacturers would be unlikely to use gold in their MEMS products.